1. Field of the Invention
The present invention relates to a processor apparatus for performing desired processing in accordance with a program, more particularly a processor apparatus which can eliminate an overhead at the time of branching and returning of processing to a program module of a lower hierarchy, such as a macro command program, and can efficiently perform desired processing at a high speed, and to an integrated circuit such as an application-specific IC built in such a processor apparatus.
2. Description of the Related Art
In a so-called microprocessor unit (MPU) (hereinafter, also simply referred to as a processor) for performing desired processing in accordance with a program, a variety of high speed architectures have been developed and operating frequencies made to higher in recent years. Processing speeds have consequently become much faster.
Also, along with advances made in semiconductor technology, it has become relatively easy to form a desired circuit including a processor on a single semiconductor circuit (IC). So-called application-specific ICs (ASIC) capable of efficiently performing desired processing at a high speed by an exclusive circuit including a processor and specifically optimized for the processing have been developed and put into use.
In such processors, however, the processing speeds of the buses and peripheral circuits for supplying programs and data to the processors have fallen behind the processing speeds of the processors resulting in the so-called bus-neck or memory-neck state. As a result, the processing ability of the processors cannot be fully used.
Therefore, attempts have been made to improve the efficiency of execution of programs by providing a large number of pre-fetch queues and instruction caches etc. for, for example, reading in advance the programs.
Summarizing the problem to be solved by the present invention, even in such a processor, for example, when a branch instruction appears, the pre-fetched program cannot be used and it becomes necessary to newly fetch the branched program, so there is a disadvantage that the processing of the processor is kept waiting and therefore the processing efficiency declines.
Recently, especially, there have been many programs of a hierarchical structure making liberal use of functions, sub-routines, macro commands, etc., with the actual execution program level being the functions. When executing such a program, it is necessary to transfer control of processing between a main program and a lower level processing module or between a processing module and further lower level processing module, so an overhead arises at that time. This has been an obstacle in improving the processing efficiency.
An object of the present invention is to provide a processor apparatus which can eliminate the overhead at the time when a branch condition arises or switching of a processing module occurs and can more efficiently perform the desired processing.
Another object of the present invention is to provide an integrated circuit having such a processor capable of efficiently performing desired processing at a high speed.
To attain the above objects, according to a first aspect of the present invention, there is provided a processor apparatus comprising a plurality of prefetching means for successively prefetching a series of instructions; a plurality of pre-decoders provided corresponding to the plurality of prefetching means and for detecting from the series of prefetched instructions an instruction by which at least a processing order becomes discontinuous; a prefetching control means for making another prefetching means, different from a prefetching means corresponding to a pre-decoder detecting an instruction by which the processing order becomes discontinuous, prefetch a new series of instructions which is not continuous with the series of instruction; a selection means for successively selecting pre-decoders having instructions to be executed from the plurality of pre-decoders and successively reading the instructions; and a processor means for executing predetermined processing in accordance with the read instructions.
In the processor apparatus configured as above, a series of instructions in an execution program are successively prefetched by one of the prefetch means, pre-decoded in a corresponding pre-decoder, and supplied to a processor means via a selection means where the desired processing is performed. At this time, when an instruction by which at least the processing order becomes discontinuous is detected in a pre-decoder, a new series of instructions based on the instruction are successively prefetched by another prefetch means and pre-decoded in a pre-decoder. When branching occurs due to the execution of an instruction, a new series of instructions are immediately supplied to the processor means only by switching the pre-decoder by the selection means.
According to a second aspect of the present invention, there is provided an integrated circuit comprising a first prefetching means for successively prefetching a series of instructions comprising a main program for executing desired processing while suitably calling up program modules; a plurality of second prefetching means for successively prefetching a series of instructions comprising a plurality of the program modules for respectively performing predetermined processing; a plurality of pre-decoders provided corresponding to the first prefetching means and the plurality of second prefetching means for detecting an instruction to call up at least the program modules from the series of prefetched instructions; a prefetching control means for making another prefetching means, different from a prefetching means corresponding to a pre-decoder detecting an instruction to call up the program modules, prefetch the called up new program modules; a selection means for successively selecting pre-decoder having instructions to be executed from the plurality of pre-decoders and successively reading the instructions; and a processor means for executing predetermined processing in accordance with the read instructions.